DATASHEET
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
Description
The ICS527-04 Clock Slicer is the most flexible way to
generate an output clock from an input clock with zero
skew. The user can easily configure the device to
produce nearly any output clock that is multiplied or
divided from the input clock. The part supports
non-integer multiplications and divisions. Using
Phase-Locked Loop (PLL) techniques, the device
accepts an input clock up to 200 MHz and produces an
output clock up to 160 MHz.
The ICS527-04 aligns rising edges on PECLIN with
FBPECL at a ratio determined by the reference and
feedback dividers.
For other PECL output clocks, see the ICS507-01,
ICS525-03, or the MK3707. For PECL in and CMOS
out, see the ICS527-02. For CMOS in and PECL out
with zero delay, use the ICS527-03.
ICS527-04
Features
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Packaged as 28-pin SSOP (150 mil body)
Synchronizes fractional clocks rising edges
CMOS in to PECL out
PECL in to PECL out
Pin selectable dividers
Zero input to output skew
User determines the output frequency - no software
needed
Slices frequency or period
Input clock frequency of 1.5 MHz - 200 MHz
Output clock frequencies up to 160 MHz
Very low jitter
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low power CMOS process
Block Diagram
R6:R0
7
PECLIN
PECLIN
Divide
by 2
1
0
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
Divide
by 2
1
0
Feedback
Divider
2
VCO
Output
Divider
2
VDD
RES
560 ohm
VDD
VDD
68 ohm
PECLO
180 ohm
VDD
68 ohm
PECLO
180 ohm
7
F6:F0
GND
2
S1:S0
FBPECL
FBPECL
IRANGE
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
1
ICS527-04
REV F 051310
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
