ICS508
PECL TO CMOS CONVERTER
PECL TO CMOS TRANSLATOR
Pin Assignment
VDDP
PECLIN
PECLIN
GND
1
2
3
4
8
7
6
5
VDDC
CLK
GND
OE
8 Pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
VDDP
PECLIN
PECLIN
GND
OE
GND
CLK
VDDC
Pin
Type
Output
Input
Input
Power
Input
Power
Output
Power
Pin Description
Connect to 3.3V or 5V. Supplies PECL input buffer.
Complementary PECL clock input.
PECL clock input.
Connect to ground.
Output enable. Tri-states CLK output when low. Internal pull-up to
VDDC.
Connect to ground.
Clock output.
Connect to 2.5 V, or 3.3 V, or 5 V. Supplies output buffer and OE pin.
External Components
The ICS508 requires two 0.01µF decoupling capacitors to be connected between VDDP and GND and
between VDDC and GND. They must be connected close to the ICS508 to minimize lead inductance. A
33Ω series terminating resistor can be used next to the CLK pin.
IDT™ / ICS™
PECL TO CMOS CONVERTER
2
ICS508
REV H 051310
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
