ICS507-01
PECL CLOCK SYNTHESIZER
PECL MULTIPLIER
Pin Assignment
X1/ICLK
VDD
VDD
S1
GND
GND
NC
PECL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
NC
S0
OE
NC
NC
RES
PECL
Clock Multiplier Select Table
S1 S0
0
0
0
M
M
M
1
1
0
M
1
0
M
1
0
M
Multiplier
9.72X*
10X
12X
6.25X
8X
5X
2X
3X
16 Pin (150 mil) SOIC
* At 3.3V, use this selection to get 155.52 MHz from a
16 MHz input.
For lowest phase noise generation of 155.52 MHz, use
a 19.44 MHz crystal and the 8X selection.
1
1
4X
0 = connect pin directly to ground
1 = connect pin directly to VDD
M = leave unconnected (floating)
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
XI/ICLK
VDD
VDD
S1
GND
GND
NC
PECL
PECL
RES
NC
NC
OE
S0
NC
X2
Type
Input
Power
Power
Input
Power
Power
—
Output
Output
Input
—
—
Input
Input
—
Output
Description
Crystal Connection. Connect to a fundamental parallel mode crystal, or
clock.
Connect to +3.3 V or 5 V, and to VDD on pin 3.
Connect to VDD on pin 2. Decouple with pin 5.
Multiplier select pin 1. Determines output frequency per table above.
Connect to ground.
Connect to ground.
No connect. Do not connect this pin to anything.
PECL output. Connect to resistor load as shown on page 1.
Complimentary PECL output. Connect to resistor load as shown on
page 1.
Bias resistor input. Connect a resistor between this pin and VDD.
No connect. Do not connect this pin to anything.
No connect. Do not connect this pin to anything.
Output Enable. Tri-states both outputs when low. Internal pull-up.
Multiplier select pin 0. Determines output frequency per table above.
No connect. Do not connect this pin to anything.
Crystal Connection. Connect to crystal, or leave unconnected for clock
input.
IDT™ / ICS™
PECL CLOCK SYNTHESIZER
2
ICS507-01
REV I 041905
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
