ICS487-25
QUAD PLL FOR DTV
CLOCK SYNTHESIZER
Pin Assignment
X1/ICLK
S0
S1
48M
VDD
GND
20M
24.576M
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
VDD
PDTS
GND
VDD
GND
33.0M
ACLK
ACLK Output Selection Table
S1
0
0
1
1
S0
0
1
0
1
ACLK (MHz)
18.432
16.9344
12.288
18.432
Note: When S1 and S0 are switched, all other output
clocks will remain stable throughout the transition.
16 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
X1/ICLK
S0
S1
48M
VDD
GND
20M
24.576M
ACLK
33.0M
GND
VDD
GND
PDTS
VDD
X2
Pin
Type
Input
Input
Input
Output
Power
Power
Output
Output
Output
Output
Power
Power
Power
Input
Power
Input
Pin Description
Crystal connection. Connect to 27 MHz crystal or clock input.
Select pin 0. Determines ACLK output frequency per table above.
Internal pull up resistor.
Select pin 1. Determines ACLK output frequency per table above.
Internal pull up resistor.
48 MHz clcok output. Weak internal pull-down when tri-state.
Connect to +3.3 V.
Connect to ground.
20 MHz clock output. Weak internal pull-down when tri-state.
24.576 MHz clock output. Weak internal pull-down when tri-state.
Audio clock output. Determined by table above. Weak internal
pull-down when tri-state
33.0 MHz clock output. Weak internal pull-down when tri-state.
Connect to ground.
Connect to +3.3 V.
Connect to ground.
Powers down entire chip and tri-states outputs when low. Internal
pull-up resistor.
Connect to +3.3 V.
Connect to 27 MHz crystal or float for clock input.
IDT™ / ICS™
QUAD PLL FOR DTV
2
ICS487-25
REV B 092109
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
