DATASHEET
QUAD PLL FOR DTV
Description
The ICS487-25 generates five high-quality,
high-frequency clock outputs. It is designed to replace
crystals and crystal oscillators in DTV applications.
Using IDT’s patented Phase Locked Loop (PLL)
techniques, the device runs from a lower frequency
crystal or clock input.
Because there is zero ppm frequency synthesis error on
the audio clocks, the audio will remain locked to the
video.
ICS487-25
Features
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Packaged in 16-pin TSSOP (Pb-free)
Replaces multiple crystals and oscillators
Input crystal or clock frequency of 27 MHz
Zero ppm frequency synthesis error
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low power CMOS process
Block Diagram
VDD
3
2
S1:0
PLL1
ACLK
20M
PLL2
48M
PLL3
33.0M
27 MHz
clock or
crystal
input
X1/ICLK
X2
Crystal
Oscillator/
Clock
Buffer
PLL4
24.576M
External capacitors
may be required.
3
GND
PDTS
(all outputs and PLLs)
IDT™ / ICS™
QUAD PLL FOR DTV
1
ICS487-25
REV B 092109
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
