ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 5. Output Divider for Output 1
Divide
Value
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bits
109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 Rule
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
1
X
1
X
1
1
X
X
X
X
X
X
1
X
1
X
1
X
0
0
X
X
X
X
X
X
1
X
0
X
0
X
1
1
X
X
X
X
X
0
0
0
1
1
0
1
1
1
0
0
1
X
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
0
0
apply Rule from Divide Values 14-37
apply Rule from Divide Values 14-37
apply Rule from Divide Values 14-37
subtract 6 from the desired divide
value, convert to binary, invert, and
apply to bits 102..98
set bits [97..95] = 100
36
37
38
39
1029
1030
1032
2056
2058
2060
2064
4112
4116
4120
4128
8224
8232
…
…
…
…
X
X
0
0
X
X
0
0
X
X
0
0
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(increments of 1)
1
1
1
0
1
1
0
1
1
(increments of 2)
1
1
1
1
1
1
0
1
1
0
1
1
(increments of 4)
1
1
1
1
1
1
0
1
1
0
1
1
(increments of 8)
1
1
1
1
1
1
output divide =
((([109..101]+3)*2)+[98])*2^[100..99]
set bits [95..97] = 101
set bits [95..97] = 101
†
(
†
this Rule applies to Divide Values
38-8232)
IDT™ / ICS™
SERIALLY PROGRAMMABLE CLOCK SOURCE
5
ICS307-03
REV J 090209
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
