ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
AC Electrical Characteristics
VDD = 3.3 V 0.3 V, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
F
Fundamental crystal
Clock
3
27
MHz
MHz
IN
0.1
300
Clock Output Frequency
F
5 pF load
0.0002
0.0002
270
200
MHz
MHz
ns
OUT
15 pF load
Output Clock Rise/Fall Time
Output Clock Duty Cycle
t
t
20 to 80% (5 pF load)
Output Divides <> 3
Output Divide = 3
1.5
R, F
45
40
49-51
55
60
10
%
%
Frequency Transition time
STROBE high to CLK
out
3
ms
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Note 2
50
ps
ps
t
Deviation from mean,
Note 2
120
ja
VCO Frequency
Divider 1 Input
VCO
100
730
540
MHz
MHz
F
Output divider 1 = 2
(5 pF load)
Output divider 1 = 2
(15 pF load)
400
720
600
570
730
540
400
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Output divider 1 = 3
(5 pF load)
Output divider 1 = 3
(15 pF load)
Output divider 1 = 38
~ 1029
All other Output
Divider 1 values
Divider 2 and 3 Inputs
Output divider 2, 3 = 2
(5 pF load)
Output divider 2, 3 = 2
(15 pF load)
Output divider 2, 3=12
440
500
MHz
MHz
Output divider 2, 3 =
16, 24, 28 and 32
All other Output
730
MHz
Divider 2 & 3 values
Note 1: Measured with 15 pF load.
Note 2: Jitter performance will change depending on configuration settings.
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
11
ICS307-03
REV J 090209
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
