ICS252
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Pin Assignment
SEL
VDD
X1/ICLK
X2
1
2
3
4
8
7
6
5
PDTS
GND
CLK2
CLK1
Output Clock Selection Table
SEL
0
1
CLK1 (MHz)
User
Configurable
User
Configurable
CLK2 (MHz)
User
Configurable
User
Configurable
Spread
Percentage
User
Configurable
User
Configurable
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
SEL
VDD
X1/ICLK
X2
CLK1
CLK2
GND
PDTS
Pin
Type
Input
Power
XI
XO
Output
Output
Power
Input
Connect to +3.3 V.
Pin Description
Select pin for frequency selection on CLK1 and CLK2. Internal pull-up resistor.
Connect this pin to a crystal or external clock input.
Connect this pin to a crystal, or float for clock input.
Clock1 output. Weak internal pull-down, low when power down.
Clock2 output. Weak internal pull-down, low when power down.
Connect this to ground.
Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up
resistor. The pin must be tied either directly or through the external resistor to
VDD ro GND. External resistor value must be less than 15kOhm.
External Components
The ICS252 requires a minimum number of external
components for proper operation.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance
of the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-6
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2 = 20].
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω
.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS252
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
IDT®
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 2
ICS252
REV J 052010
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
