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23S08E-5HPGG8 参数 Datasheet PDF下载

23S08E-5HPGG8图片预览
型号: 23S08E-5HPGG8
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V零延迟时钟乘法器,扩频兼容 [3.3V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE]
分类和应用: 时钟
文件页数/大小: 11 页 / 73 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT23S08E  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Rating  
Max.  
–0.5to+4.6  
–0.5to+5.5  
–0.5to  
Unit  
V
VDD  
SupplyVoltageRange  
InputVoltageRange(REF)  
InputVoltageRange  
(except REF)  
(2)  
VI  
VI  
V
1
2
16  
15  
14  
13  
12  
REF  
FBK  
V
CLKA1  
CLKA4  
CLKA3  
VDD  
VDD+0.5  
–50  
3
IIK (VI < 0)  
IO  
InputClampCurrent  
ContinuousOutputCurrent  
mA  
mA  
CLKA2  
±50  
4
5
6
VDD  
(VO = 0 to VDD)  
VDD or GND  
TA = 55°C  
(instillair)(3)  
TSTG  
GND  
CLKB1  
CLKB2  
S2  
GND  
CLKB4  
CLKB3  
S1  
ContinuousCurrent  
±100  
0.7  
mA  
W
MaximumPowerDissipation  
11  
10  
9
7
8
StorageTemperatureRange  
CommercialTemperature  
Range  
–65to+150  
0 to +70  
°C  
°C  
Operating  
Temperature  
Operating  
Temperature  
NOTES:  
IndustrialTemperature  
Range  
-40to+85  
°C  
SOIC/ TSSOP  
TOP VIEW  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect reliability.  
2. The input and output negative-voltage ratings may be exceeded if the input and output  
clamp-current ratings are observed.  
3. The maximum package power dissipation is calculated using a junction temperature  
PINDESCRIPTION  
of 150°C and a board trace length of 750 mils.  
Pin Number  
FunctionalDescription  
REF (1)  
CLKA1(2)  
CLKA2(2)  
VDD  
1
2
InputReferenceClock,5VoltTolerantInput  
Clock Output for Bank A  
Clock Output for Bank A  
3.3V Supply  
3
4
GND  
5
Ground  
CLKB1(2)  
CLKB2(2)  
S2(3)  
6
Clock Output for Bank B  
Clock Output for Bank B  
Select Input, Bit 2  
APPLICATIONS:  
• SDRAM  
• Telecom  
7
8
S1(3)  
9
Select Input, Bit 1  
• Datacom  
• PC Motherboards/Workstations  
• Critical Path Delay Designs  
CLKB3(2)  
CLKB4(2)  
GND  
10  
11  
12  
13  
14  
15  
16  
Clock Output for Bank B  
Clock Output for Bank B  
Ground  
VDD  
3.3V Supply  
CLKA3(2)  
CLKA4(2)  
FBK  
Clock Output for Bank A  
Clock Output for Bank A  
PLLFeedbackInput  
NOTES:  
1. Weak pull down.  
2. Weak pull down on all outputs.  
3. Weak pull ups on these inputs.  
2
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