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1894K-32LF 参数 Datasheet PDF下载

1894K-32LF图片预览
型号: 1894K-32LF
PDF下载: 下载PDF文件 查看货源
内容描述: 10BASE -T / 100BASE - TX集成了RMII接口PHYCEIVER [10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE]
分类和应用: 网络接口电信集成电路电信电路PC
文件页数/大小: 53 页 / 484 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin
Name
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
VSS
RESET_N
P2/INT
MDIO
MDC
AMDIX/RXD3
P3/RXD2
RXTRI/
RXD1
FDPX/
RXD0
RMII/RXDV
VDDIO
ANSEL/
RXCLK
NOD/
RXER
SPEED/
TXCLK
TXEN
TXD0
VDDD
TXD1
TXT2
TXD3
Pin
Type
1
AIO
AIO
Power
AIO
AIO
Power
AIO
Pin Description
Twisted pair port A (for either transmit or receive) positive signal
Twisted pair port A (for either transmit or receive) negative signal
3.3V Power Supply
Twisted pair port B (for either transmit or receive) negative signal
Twisted pair port B (for either transmit or receive) positive signal
3.3V Power Supply
Transmit Current bias pin, connected to Vdd and ground via resistors (see
“Recommended Component Values” table and the “ICS1894-32 TCSR” figure).
Hardware reset for the entire chip (active low)
PHY address Bit 2 as input (during power on reset/hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
Management Data Input/Output
Management Data Clock
AMDIX enable as input (during power on reset/hardware reset)
Receive data Bit 3 in MII mode as output.
PHY address Bit 3 as input (during power on reset/hardware reset)
Receive data Bit 2 in MII mode as output.
RX tri-state enable as input (during power on reset/hardware reset)
Receive data Bit 1 in both RMII and MII mode as output.
Full duplex enable as input (during power on reset/hardware reset)
Receive data Bit 0 in both RMII and MII mode as output
RMII/MII select as input (during power on reset/hardware reset)
Receive data valid in MII mode and CRS_DV in RMII mode as output.
3.3 V/1.8 V IO Power Supply.
Auto-negotiation enable as input (during power on reset/hardware reset)
Receive clock in MII mode as output.
Node/repeater select as input (during power on reset/hardware reset)
Receive error in MII/RMII mode as output
10M/100M select as input (during power on reset/hardware reset)
Transmit clock in MII mode as output
Transmit enable in RMII/MII mode
Transmit data Bit 0 in RMII/MII mode
3.3 V Power Supply
Transmit data Bit 1 in RMII/MII mode
Transmit data Bit 2 in MII mode
Transmit data Bit 3 in MII mode
Ground Connect to ground.
Ground Connect to ground.
Input
IO/Ipd
IO
Input
IO/Ipu
IO/Ipd
IO/Ipu
IO/Ipu
IO/Ipd
Power
IO/Ipu
IO/Ipd
IO/Ipu
Input
Input
Power
Input
Input
Input
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
3
ICS1894-32
REV G 020509