ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Block Diagram
100Base-T
10/100 MII/RMII
MAC
Interface
Interface
MUX
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Smart Power
Control
Block
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
Pin Assignment
P1/LED1
P0/LED0
REFOUT
REFIN
VDDD
25
TXD3
TXD2
TXD1
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
1
TXD0
TXEN
SPEED/TXCLK
NLG32 With Ground
Connecting to Thermal Pad
NOD/RXER
ANSEL/RXCLK
VDDIO
RMII/RXDV
FDPX/RXD0
9
17
VSS
MDC
AMDIX/RXD3
RESET_N
P2/INT
MDIO
P3/RXD2
32-pin 5mm x 5mm QFN
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
RXTR1RXD1
2
ICS1894-32
REV G 020509
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
