ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin
Number
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin
Name
SPEED/
TXCLK
TXEN
TXD0
VDDD
LED3
TXD1
TXT2
TXD3
REF_OUT
REF_IN
P4/LED2
P0/LED0
P1/ISO/LED1
Pin
Type
IO/Ipu
Input
Input
Power
IO/Ipd
Input
Input
Input
Input
IO/Ipu
IO
IO
Pin Description
10M/100M select as input (during power on reset and hardware reset)
Transmit clock as output in MII mode
Transmit enable for both RMII and MII modes
Transmit data Bit 0 for both RMII and MII modes
Core Power Supply
LED3 output
Transmit data Bit 1for both RMII and MII modes
Transmit data Bit 2 for MII mode
Transmit data Bit 3 for MII mode
25 MHz crystal (or clock) input for MII mode. 50MHz clock input for RMII mode
PHY address Bit 4 as input (during power on reset and hardware reset)
and LED # 2 as output
PHY address Bit 0 as input (during power on reset and hardware reset) and LED #
0(function configurable, default is "activity/no activity") as output
PHY address Bit 1 as input (during power on reset and hardware reset) and LED #
1 (function configurable, default is "10/100 mode") as output
Output 25 MHz crystal output
Notes:
1. AIO: Analog input/output PAD.
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is
asserted, two bits of recovered data are sent from the PHY to the MAC.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is
asserted, two bits of data are received by the PHY from the MAC.
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
4
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
