ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Pin
Name
AMDIX
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
VSS
RESET_N
P2/INT
MDIO
MDC
VDDIO
HWSW/
CRS
Regpin/
COL
AMDIX/RXD3
P3/RXD2
RXTRI/
RXD1
SI/LED4
FDPX/
RXD0
RMII/RXDV
SPEED
TXER
ANSEL/
RXCLK9
NOD/
RXER
Pin
Type
IN/Ipu
AIO
AIO
Power
AIO
AIO
Power
AIO
Input
IO/Ipd
IO
Input
Power
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipd
Ipu
IN
IO/Ipu
IO/Ipd
AMDIX Enable
Pin Description
Twisted pair port A (for either transmit or receive) positive signal
Twisted pair port A (for either transmit or receive) negative signal
3.3V Power Supply
Twisted pair port B (for either transmit or receive) negative signal
Twisted pair port B (for either transmit or receive) positive signal
3.3V Power Supply
Transmit Current bias pin, connected to Vdd and ground via two resistors.
Hardware reset for the whole chip (active low)
PHY address Bit 2 as input (during power on reset and hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
Management Data Input/Output
Management Data Clock
3.3 V IO Power Supply.
Hardware/Software control for phy speed as input (during power on reset and
hardware reset) and CRS output in MII mode.
Full register access enable as input (during power on reset and hardware reset) and
COL output in MII mode
AMDIX hardware enable as input (during power on reset and hardware reset)
Receive data Bit 3 as output in MII mode
PHY address Bit 3 as input (during power on reset and hardware reset)
Receive data Bit 2 as output in MII mode
RX isolate enable (during power on reset and hardware reset)
Received data Bit 1 as output in both RMII and MII modes
MII/SI mode select as input (during power on reset and hardware reset) and
LED #4 as output
Full duplex enable (during power on reset and hardware reset)
Received data Bit 0 as output in both RMII and MII modes.
RMII/MII select as input (during power on reset and hardware reset)
Receive data valid in MII mode and CRS_DV in RMII mode as output
10/100M input select. 1 = 100M mode, 0 = 10M mode.
TXER Input
Auto-negotiation enable(during power on reset and hardware reset)
Receive clock as output in MII mode
Node/repeater select (during power on reset and hardware reset)
Receive error as output in MII mode
Ground Connect to ground.
Ground Connect to ground.
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
3
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
