ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Bit
Definition
When Bit = 0
When Bit = 1
Access 2 SF2
Default3
Hex
Register 25h - Extended Control Register
25.15:12
25.11
25.10
25.9
Reserved
Reserved
RW
RW
RW
RW
0
0
1
1
0
0
0
6
Reserved
Reserved
Add_Bias
Disable
Enable
TX10BIAS_SET
The normal output current of the Bias block for
10BaseT is 540uA. Changing the register can modify
the current with a step size of 5%
000: output 80% current
25.8
25.7
4
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
25.6
25.5
25.4
TX100BIAS_SET
The normal output current of the Bias block for
100BaseTX is 180uA. Changing the register can
modify the current with a step size of 5%
000: output 80% current
RW
1
0
0
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
25.3
25.2
OUTDLY_CTL
RX_SET
This register controls the delay time of the digital
control signal for xmit_dac.
00: Longest delay time (same as original design)
01: Long delay time
10: Short delay time
11: Shortest delay time
RW
RW
0
1
25.1
25.0
The output current of Bias block for RX block is
108µA. The register can change the current with a
step about 16.5%
0
1
00: Output 83.5% current
01: Output 100% current
10: Output 116.5% current
11: Output 133% current
Changing this value may modify the RX block
performance
Register 26 - 31h - Extended Control Register (Reserved)
Note 1:
Note 2:
Ignored if Auto negotiation is enabled.
CW = Command Override Write
LH = Latching High
LL = Latching Low
LMX = Latching Maximum
RO = Read Only
RW = Read/Write
RW/0 = Read/Write Zero
RW/1 = Read/Write One
SC = Self-clearing
SF = Special Functions
L = Latched on power-up/hardware reset
Note 3:
‡ Whenever the PHY address is equal to 00000 (binary), the Isolate bit 0.10 is logic one, whenever the PHY address Is not equal to 00000, the Isolate bit 0.10 is logic
zero.
† As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
28
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
