ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
MII Signal Definition
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information.
MII Signal Name
Direction
(with respect to PHY,
ICS1894-40 signal)
Output
Input
Input
Output
Output
Output
Output
Output
Output
Direction
(with respect to MAC)
Input
Output
Output
Input
Input
Input
Input, or (not required)
Input
Input
Description
TXCLK
TXEN
TXD[3:0]
RXCLK
RXDV
RXD[3:0]
RXER
CRS
COL
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
Transmit Enable
Transmit Data [3:0]
Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
Receive Data Valid
Receive Data [3:0]
Receive Error
Carrier Sense
Collision Detection
Transmit Clock (TXCLK)
TXCLK is sourced by the PHY. It is a continuous clock that
provides the timing reference for TXEN and TXD[3:0].
TXCLK is 2.5MHz for 10Mbps operation and 25MHz for
100Mbps operation.
•
In 10Mbps mode, RXCLK is recovered from the line while
carrier is active. RXCLK is derived from the PHY’s
reference clock when the line is idle, or link is down.
•
In 100Mbps mode, RXCLK is continuously recovered
from the line. If link is down, RXCLK is derived from the
PHY’s reference clock.
RXCLK is 2.5MHz for 10Mbps operation and 25MHz for
100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0]
for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all
nibbles to be transmitted are presented on the MII, and is
negated prior to the first TXCLK following the final nibble of
a frame. TXEN transitions synchronously with respect to
TXCLK.
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is
presenting recovered and decoded nibbles on RXD[3:0].
•
In 10Mbps mode, RXDV is asserted with the first nibble of
the SFD (Start of Frame Delimiter), “5D”, and remains
asserted until the end of the frame.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXCLK.
When TXEN is asserted, TXD[3:0] are accepted for
transmission by the PHY. TXD[3:0] is ”00” to indicate idle
when TXEN is de-asserted. Values other than “00” on
TXD[3:0] while TXEN is de-asserted are ignored by the
PHY.
•
In 100Mbps mode, RXDV is asserted from the first nibble
of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXCLK.
Receive Data [3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC.
For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
Receive Clock (RXCLK)
RXCLK provides the timing reference for RXDV, RXD[3:0],
and RXER.
IDT™ / ICS™
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 8
ICS1894-40
REV C 092909
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
