ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Strapping Options
Pin
Number
1
16
17
18
38
19
12
40
39
21
20
22
Pin
Name
AMDIX
HWSW/CRS
REGPIN/COL
AMDIX/RXD2
P4/LED2
P3/RXD2
P2/INT
P1/LED1
P0/LED0
SI/LED4
RXTRI/RXD1
FDPX/RXD0
Pin
Type
1
IN/Ipu
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipu
IO/Ipd
IO/Ipd
IO/
IO/
IO/Ipd
IO/Ipd
IO/Ipu
1 = AMDIX enable
0 = AMDIX disable
Pin Function
Hardware pin select enable. Active during power-on and hardware reset.
Full register access enable. Active during power-on and hardware reset.
1 = AMDIX enable
0 = AMDIX disable
The PHY address is set by P[4:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
MII/SI mode select.
Active during power-on and hardware reset.
1=RX tri-state for MII/RMII interface
0=RX output enable
1=Full duplex
0=Half duplex
Ignored if Auto negotiation is enabled
[1x]=RMII mode
[01]=SI mode (Serial interface mode)
[00]=MII mode
1=100M mode
0=10M mode
1=Enable auto negotiation
0=Disable auto negotiation
0=Node mode
1=repeater mode
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
LED3 output
23
RMII/RXDV
IO/Ipd
24
26
27
28
SPEED
ANSEL/RXCLK
NOD/RXER
SPEED/TXCLK
IO/Ipu
IO/Ipu
IO/Ipd
IO/Ipu
32
LED3
IO/Ipu
1.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
Functional Description
The ICS1894-32 is a stream processor. During data
transmission, it accepts sequential nibbles from its MAC
(Media Access Control) converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-32 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles. It
subsequently presents these nibbles to its MAC Interface.
The ICS1894-32 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
•
Physical Coding sublayer (PCS)
IDT™ / ICS™
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 5
ICS1894-40
REV C 092909
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
