ICS1893CF Data Sheet - Release
Chapter 7 Management Register Set
7.3.12 Jabber Detect (bit 1.1)
The purpose of this bit is to allow an STA to determine if the ICS1893CF detects a Jabber condition as
defined in the ISO/IEC specification.The ICS1893CF Jabber Detection function is controlled by the Jabber
Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the ICS1893CF
Jabber Detection function must be enabled. When bit 18.5 is logic:
• Zero, the ICS1893CF disables Jabber Detection and sets the Jabber Detect bit to logic zero.
• One, the ICS1893CF enables Jabber Detection and sets the Jabber Detect bit to logic one upon
detection of a Jabber condition. When no Jabber condition is detected, the Jabber Detect bit is not
altered.
Note:
1. The Jabber Detect bit is accessible through both the Status register (as bit 1.1) and the QuickPoll
Detailed Status Register (as bit 17.2). A read of either register clears the Jabber Detect bit.
2. The Jabber Detect bit is a latching high (LH) bit. (For more information on latching high and latching low
bits, see Section 7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)
7.3.13 Extended Capability (bit 1.0)
The STA reads bit 1.0 to determine if the ICS1893CF has an extended register set. In the ICS1893CF this
bit is always logic one, indicating that it has extended registers.
ICS1893CF, Rev. J, 08/11/09
August, 2009
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
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