ICS1893CF Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 9-19 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
Figure 9-13 shows the timing diagram for the time periods.
Table 9-19. 10M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Time
Period
Parameter
Condi- Min. Typ. Max. Units
tions
t1
t2
TXEN Asserted to CRS Assert
0
0
–
2
2
4
Bit times
Bit times
TXEN De-Asserted to CRS De-Asserted
Figure 9-13. 10M MII Carrier Assertion/De-Assertion Timing Diagram
(Half-Duplex Transmission Only)
t2
TXEN
TXCLK
CRS
t1
ICS1893CF, Rev. J, 08/11/09
August, 2009
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
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