ICS1893CF Data Sheet Rev. J - Release
Chapter 9 DC and AC Operating Conditions
9.5.7 MII Management Interface Timing
Table 9-14 lists the significant time periods for the MII Management Interface timing (which consists of
timings of signals on the MDC and MDIO pins). Figure 9-8 shows the timing diagram for the time periods.
Table 9-14. MII Management Interface Timing
Time
Parameter
Conditions Min.
Typ.
Max. Units
Period
t1
t2
t3
t4
t5
t6
MDC Minimum High Time
–
–
–
–
–
–
160
160
400†
0
–
–
†
–
–
–
–
–
ns
ns
ns
ns
ns
ns
MDC Minimum Low Time
MDC Period
–
MDC Rise Time to MDIO Valid
MDIO Setup Time to MDC
MDIO Hold Time after MDC
300
–
10
10
–
† The ICS1893CF is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading
of MDC.
Figure 9-8. MII Management Interface Timing Diagram
MDC
t1
t2
t3
t4
MDIO
(Output)
MDC
MDIO
(Input)
t5
t6
ICS1893CF, Rev. J, 08/11/09
August, 2009
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
109
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