ICS1893BY-10
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
ICS1893BY-10 Data Sheet - Release
TSD
Table of Contents
Table of Contents
Section
9.5.10
9.5.11
9.5.12
9.5.13
9.5.14
9.5.15
9.5.16
9.5.17
9.5.18
9.5.19
9.5.20
9.5.21
9.5.22
Chapter 10
Chapter 11
Title
Page
10M Serial Interface: Transmit Latency ...............................................................128
10M Media Independent Interface: Transmit Latency ..........................................129
MII / 100M Stream Interface: Transmit Latency ...................................................130
100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) ...............131
10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) .................132
100M MII / 100M Stream Interface: Receive Latency ..........................................133
100M Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion .......134
Reset: Power-On Reset .......................................................................................135
Reset: Hardware Reset and Power-Down ...........................................................136
10Base-T: Heartbeat Timing (SQE) .....................................................................137
10Base-T: Jabber Timing .....................................................................................138
10Base-T: Normal Link Pulse Timing ..................................................................139
Auto-Negotiation Fast Link Pulse Timing .............................................................140
Physical Dimensions of ICS1893BY-10 Package...................................................... 141
Ordering Information..................................................................................................... 142
ICS1893BY-10 Rev A 3/24/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8
8
March, 2004
ICS1893BY-10
IDT™ / ICS™
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
