ICS1893BY-10
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
ICS1893BY-10 - Release
TSD
Table of Contents
Table of Contents
Section
7.14
7.14.1
7.14.2
7.14.3
7.14.4
7.14.5
7.14.6
7.14.7
7.14.8
Chapter 8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Chapter 9
9.1
9.2
9.3
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
Title
Page
Register 19: Extended Control Register 2 .............................................................95
Node/Repeater Configuration (bit 19.15) ...............................................................96
Hardware/Software Priority Status (bit 19.14) ........................................................96
Remote Fault (bit 19.13) ........................................................................................96
ICS Reserved (bits 19.12:8) ...................................................................................96
Auto-MDI/MDIX (bits 19. 9:8) (New) ......................................................................96
Twisted Pair Tri-State Enable, TPTRI (bit 19.7)......................................................97
ICS Reserved (bits 19.6:1) .....................................................................................97
Automatic 100Base-TX Power-Down (bit 19.0) .....................................................97
Pin Diagram, Listings, and Descriptions ....................................................................... 98
ICS1893BY-10 Pin Diagram ..................................................................................98
ICS1893BY-10 Pin Listings ....................................................................................99
ICS1893BY-10 Pin Descriptions ..........................................................................100
Transformer Interface Pins ..................................................................................100
Multi-Function (Multiplexed) Pins: PHY Address and LED Pins ..........................101
Configuration Pins ................................................................................................104
MAC/Repeater Interface Pins ..............................................................................106
Reserved Pins ......................................................................................................114
Ground and Power Pins .......................................................................................114
DC and AC Operating Conditions................................................................................. 115
Absolute Maximum Ratings .................................................................................115
Recommended Operating Conditions ..................................................................115
Recommended Component Values .....................................................................116
DC Operating Characteristics ..............................................................................117
DC Operating Characteristics for Supply Current ................................................117
DC Operating Characteristics for TTL Inputs and Outputs ..................................117
DC Operating Characteristics for REF_IN ...........................................................118
DC Operating Characteristics for Media Independent Interface ..........................118
Timing Diagrams ..................................................................................................119
Timing for Clock Reference In (REF_IN) Pin .......................................................119
Timing for Transmit Clock (TXCLK) Pins .............................................................120
Timing for Receive Clock (RXCLK) Pins ..............................................................121
100M MII / 100M Stream Interface: Synchronous Transmit Timing .....................122
10M MII: Synchronous Transmit Timing ..............................................................123
MII / 100M Stream Interface: Synchronous Receive Timing ................................124
MII Management Interface Timing .......................................................................125
10M Serial Interface: Receive Latency ................................................................126
10M Media Independent Interface: Receive Latency ...........................................127
ICS1893BY-10 Rev A 3/24/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
7
7
March, 2004
ICS1893BY-10
IDT™ / ICS™
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
