ICS1893BF Data Sheet Rev. E - Release
Chapter 9 DC and AC Operating Conditions
9.5.16 Reset: Hardware Reset and Power-Down
Table 9-23 lists the significant time periods for the hardware reset and power-down reset. The time periods
consist of timings of signals on the following pins:
• REF_IN
• RESETn
• TXCLK
Figure 9-17 shows the timing diagram for the time periods.
Table 9-23. Hardware Reset and Power-Down Timing
Time
Period
Parameter
Condi-
tions
Min. Typ. Max. Units
t1
t2
t3
RESETn Active to Device Isolation and Initialization
Minimum RESETn Pulse Width
–
–
–
–
500
–
60
40
35
–
–
ns
ns
RESETn Released to TXCLK Valid
500
ms
Figure 9-17. Hardware Reset and Power-Down Timing Diagram
REF_IN
RESETn
t1
t2
t3
TXCLK Valid
Power
Consumption
(AC only)
ICS1893BF, Rev. E, 8/11/09
August, 2009
Copyright © 2009, IDT, Inc.
All rights reserved.
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