ICS1893BF Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.15 Reset: Power-On Reset
Table 9-22 lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
• VDD
• TXCLK
Figure 9-16 shows the timing diagram for the time periods.
Table 9-22. Power-On Reset Timing
Time
Period
Parameter
Conditions
Min.
Typ.
Max. Units
500 ms
t1
VDD ≥ 2.7 V to Reset Complete
–
40
45
Figure 9-16. Power-On Reset Timing Diagram
2.7 V
VDD
t1
TXCLK
Valid
ICS1893BF, Rev. E, 8/11/09
August, 2009
Copyright © 2009, IDT, Inc.
All rights reserved.
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