欢迎访问ic37.com |
会员登录 免费注册
发布采购

1893CF 参数 Datasheet PDF下载

1893CF图片预览
型号: 1893CF
PDF下载: 下载PDF文件 查看货源
内容描述: [Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 MM INCH, SSOP-48]
分类和应用: 网络接口电信集成电路电信电路光电二极管
文件页数/大小: 136 页 / 1040 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
 浏览型号1893CF的Datasheet PDF文件第16页浏览型号1893CF的Datasheet PDF文件第17页浏览型号1893CF的Datasheet PDF文件第18页浏览型号1893CF的Datasheet PDF文件第19页浏览型号1893CF的Datasheet PDF文件第21页浏览型号1893CF的Datasheet PDF文件第22页浏览型号1893CF的Datasheet PDF文件第23页浏览型号1893CF的Datasheet PDF文件第24页  
ICS1893AF Data Sheet - Release  
Chapter 5 Operating Modes Overview  
5.1.2 Specific Reset Operations  
This section discusses the following specific ways that the ICS1893AF can be reset:  
Hardware reset (using the RESETn pin)  
Power-on reset (applying power to the ICS1893AF)  
Software reset (using Control Register bit 0.15)  
Note: At the completion of a reset (either hardware, power-on, or software), the ICS1893AF sets all  
registers to their default values.  
5.1.2.1 Hardware Reset  
Entering Hardware Reset  
Holding the active-low RESETn pin low for a minimum of five REF_IN clock cycles initiates a hardware  
reset (that is, the ICS1893AF enters the reset state). During reset, the ICS1893AF executes the steps  
listed in Section 5.1.1.1, “Entering Reset”.  
Exiting Hardware Reset  
After the signal on the RESETn pin transitions from a low to a high state, the ICS1893AF completes in 640  
ns (that is, in 16 REF_IN clocks) steps 1 through 5, listed in Section 5.1.1.2, “Exiting Reset”. After the first  
five steps are completed, the Serial Management Port is ready for normal operations, but this action does  
not signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and  
receive clock (RXCLK) are available, which is typically 53 ms after the RESETn pin goes high. [For details  
on this transition, see Section 10.5.16, “Reset: Hardware Reset and Power-Down”.]  
Note:  
1. The MAC/Repeater Interface is not available for use until the TXCLK and RXCLK are valid.  
2. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit  
that is used to initiate a software reset.  
5.1.2.2 Power-On Reset  
Entering Power-On Reset  
When power is applied to the ICS1893AF, it waits until the potential between VDD and VSS achieves a  
minimum voltage before entering reset and executing the steps listed in Section 5.1.1.1, “Entering Reset”.  
After entering reset from a power-on condition, the ICS1893AF remains in reset for approximately 20 µs.  
(For details on this transition, see Section 10.5.15, “Reset: Power-On Reset”.)  
Exiting Power-On Reset  
The ICS1893AF automatically exits reset and performs the same steps as for a hardware reset. (See  
Section 5.1.1.2, “Exiting Reset”.)  
Note: The only difference between a hardware reset and a power-on reset is that during a power-on  
reset, the ICS1893AF isolates its RESETn input pin. All other functionality is the same. As with a  
hardware reset, Control Register bit 0.15 does not represent the status of a power-on reset.  
ICS1893AF
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
20  
 复制成功!