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1893CF 参数 Datasheet PDF下载

1893CF图片预览
型号: 1893CF
PDF下载: 下载PDF文件 查看货源
内容描述: [Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 MM INCH, SSOP-48]
分类和应用: 网络接口电信集成电路电信电路光电二极管
文件页数/大小: 136 页 / 1040 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS1893AF Data Sheet - Release  
Chapter 5 Operating Modes Overview  
5.1.2.3 Software Reset  
Entering Software Reset  
Initiation of a software reset occurs when a management entity writes a logic one to Control Register bit  
0.15. When this write occurs, the ICS1893AF enters the reset state for two REF_IN clock cycles.  
Note: Entering a software reset is nearly identical to entering a hardware reset or a power-on reset,  
except that during a software-initiated reset, the ICS1893AF does not enter the power-down state.  
Exiting Software Reset  
At the completion of a reset (either hardware, power-on, or software), the ICS1893AF sets all registers to  
their default values. This action automatically clears (that is, sets equal to logic zero) Control Register bit  
0.15, the software reset bit. Therefore, for a software reset (only), bit 0.15 is a self-clearing bit that indicates  
the completion of the reset process.  
Note:  
1. The RESETn pin is active low but Control Register bit 0.15 is active high.  
2. Exiting a software reset is nearly identical to exiting a hardware reset or a power-on reset, except that  
upon exiting a software-initiated reset, the ICS1893AF does not re-latch its Serial Management Port  
Address into the Extended Control Register. [For information on the Serial Management Port Address,  
see Section 8.11.3, “PHY Address (bits 16.10:6)”.]  
3. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit  
that is used to initiate a software reset. During a hardware or power-on reset, Control Register bit 0.15  
does not get set to logic one. As a result, this bit 0.15 cannot be used to indicate the completion of the  
reset process for hardware or power-on resets.  
5.2 Power-Down Operations  
The ICS1893AF enters the power-down state whenever either (1) the RESETn pin is low or (2) Control  
Register bit 0.11 (the Power-Down bit) is logic one. In the power-down state, the ICS1893AF disables all  
internal functions and drives all MAC/Repeater Interface output pins to logic zero except for those that  
support the MII Serial Management Port. In addition, the ICS1893AF tri-states its Twisted-Pair Transmit  
pins (TP_TXP and TP_TXN) to achieve an additional reduction in power.  
There is one significant difference between entering the power-down state by setting Control Register bit  
0.11 as opposed to entering the power-down state during a reset. When the ICS1893AF enters the  
power-down state:  
By setting Control Register bit 0.11, the ICS1893AF maintains the value of all Management Register bits  
except for the latching low (LL), latching high (LH), and latching maximum (LMX) status bits. Instead,  
these LL, LH, and LMX Management Register bits are re-initialized to their default values.  
During a reset, the ICS1893AF sets all of its Management Register bits to their default values. It does not  
maintain the state of any Management Register bit.  
For more information on power-down operations, see the following:  
Section 8.14, “Register 19: Extended Control Register 2”  
Section 10.4, “DC Operating Characteristics”, which has tables that specify the ICS1893AF power  
consumption while in the power-down state  
ICS1893AF,
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
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