ICS1893AF Data Sheet - Release
Chapter 9 Pin Diagram, Listings, and Descriptions
9.2.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins
Table 9-6 lists the pins for the multi-function group of pins (that is, the multiplexed PHY Address / LED pins).
Note:
1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input
that is sampled when the ICS1893AF exits the reset state. After sampling is complete, these pins are
output pins that can drive status LEDs.
2. A software reset does not affect the state of a multi-function configuration pin. During a software reset,
all multi-function configuration pins are outputs.
3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the
address of the ICS1893AF. LEDs placed in series with these resistors provide a designated status
indicator.
Caution: All pins listed in Table 9-6 must not float.
4. As outputs, the asserted state of a multi-function configuration pin is the inverse of the sense sampled
during reset. This inversion provides a signal that can illuminate an LED during an asserted state. For
example, if a multi-function configuration pin is pulled down to ground through an LED and a
current-limiting resistor, then the sampled sense of the input is low. To illuminate an LED for the
asserted state requires the output to be high.
Note: Each of these pins monitor the data link by providing signals that directly drive LEDs.
Table 9-6. PHY Address and LED Pins
Pin
Pin
Pin
Pin Description
Name Number
Type
P0AC
1
Input or PHY (Address Bit) 0 / Activity LED.
Output For more information on this pin, see Section 6.5, “Status Interface”.
• This multi-function configuration pin is:
– An input pin during either a power-on reset or a hardware reset. In
this case, this pin configures the ICS1893AF PHY address Bit 0.
– An output pin following reset. In this case, this pin provides indication
of Receive “OR” Transmit activity.
As an input pin:
• This pin establishes the address for the ICS1893AF. When the signal
on this pin is logic:
– Low, that address bit is set to logic zero.
– High, that address bit is set to logic one.
As an output pin:
• When the signal on this pin is:
– De-asserted, this state indicates the ICS1893AF does not have
activity.
– Asserted, this state indicates the ICS1893AF has activity.
Caution: This pin must not float. (See the notes at Section 9.2.2,
“Multi-Function (Multiplexed) Pins: PHY Address and LED
Pins”.)
ICS1893AF, Rev. D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
101
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
