ICS1893AF Data Sheet - Release
Chapter 8 Management Register Set
8.13 Register 18: 10Base-T Operations Register
The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893AF
activity while the ICS1893AF is operating in 10Base-T mode.
Note:
1. For an explanation of acronyms used in Table 8-20, see Chapter 1, “Abbreviations and Acronyms”.
2. During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
Table 8-20. 10Base-T Operations Register (register 18 [0x12])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De- Hex
fault
18.15 Remote Jabber
Detect
No Remote Jabber
Condition detected
Remote Jabber Condition
Detected
RO
LH
0
–
18.14 Polarity reversed
18.13 ICS reserved
18.12 ICS reserved
18.11 ICS reserved
18.10 ICS reserved
Normal polarity
Polarity reversed
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Jabber Check disabled
Read unspecified
RO
LH
–
0
–
–
–
–
–
–
–
–
0
1
0
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Normal Jabber behavior
Read unspecified
RW/0
RW/0
RW/0
RW/0
RW/0
RW/0
RW/0
RW/0
RW
–
–
–
–
0
–
18.9
18.8
18.7
18.6
18.5
18.4
18.3
ICS reserved
ICS reserved
ICS reserved
ICS reserved
Jabber inhibit
ICS reserved
–
–
–
–
–
RW/1
RW
–
Auto polarity inhibit Polarity automatically
corrected
Polarity not automatically
corrected
–
18.2
18.1
18.0
SQE test inhibit
Link Loss inhibit
Squelch inhibit
Normal SQE test behavior SQE test disabled
RW
RW
RW
–
–
–
0
0
0
Normal Link Loss behavior Link Always = Link Pass
Normal squelch behavior
No squelch
8.13.1 Remote Jabber Detect (bit 18.15)
The Remote Jabber Detect bit is provided to indicate that an ICS1893AF port has detected a Jabber
Condition on its receive path. This bit is reset to logic zero on a read of the 10Base-T operations register.
When this bit is logic:
• Zero, it indicates a Jabber Condition has not occurred on the port’s receive path since either the last read
of this register or the last reset of the associated port.
• One, it indicates a Jabber Condition has occurred on the port’s receive path since either the last read of
this register or the last reset of the associated port.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)
Note: This bit is provided for information purposes only (that is, no actions are taken by the port). The
ISO/IEC specification defines the Jabber Condition in terms of a port’s transmit path. To set this bit,
an ICS1893AF port monitors its receive path and applies the ISO/IEC Jabber criteria to its receive
path.
ICS1893AF, Rev. D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
93
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
