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1893CFI 参数 Datasheet PDF下载

1893CFI图片预览
型号: 1893CFI
PDF下载: 下载PDF文件 查看货源
内容描述: [Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 MM INCH, SSOP-48]
分类和应用: 网络接口电信集成电路电信电路光电二极管
文件页数/大小: 136 页 / 1040 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS1893AF Data Sheet - Release  
Chapter 9 Pin Diagram, Listings, and Descriptions  
Table 9-6. PHY Address and LED Pins  
Pin  
Pin  
Pin  
Pin Description  
Name Number  
Type  
P1CL 3  
Input or PHY (Address Bit) 1 / Collision LED.  
Output For more information on this pin, see Section 6.5, “Status Interface”.  
This multi-function configuration pin is:  
– An input pin during either a power-on reset or a hardware reset. In  
this case, this pin configures the ICS1893AF PHY Address Bit 1.  
– An output pin following reset. In this case, this pin provides collision  
status for the ICS1893AF.  
As an input pin:  
This pin establishes the address for the ICS1893AF. When the signal  
on this pin is Logic:  
– Low, that address bit is set to logic zero.  
– High, that address is set to logic one.  
As an output pin:  
When the signal on this pin is:  
– De-asserted, this state indicates the ICS1893AF does not detect any  
collisions.  
– Asserted, this state indicates the ICS1893AF detects collisions.  
The ICS1893AF asserts its Collision LED for a period of approximately  
70 msec when it detects a collision.  
Caution: This pin must not float. (See the notes at Section 9.2.2,  
“Multi-Function (Multiplexed) Pins: PHY Address and LED  
Pins”.)  
P2LI  
4
Input or PHY (Address Bit) 2 / Link Integrity LED.  
Output For more information on this pin, see Section 6.5, “Status Interface”.  
This multi-function configuration pin is:  
– An input pin during either a power-on reset or a hardware reset. In  
this case, this pin configures the address of the ICS1893AF PHY  
Address Bit 2.  
– An output pin following reset. In this case, this pin provides link status  
for the ICS1893AF.  
As an input pin:  
This pins establishes the address for the ICS1893AF. When the signal  
on this pin is logic:  
– Low, that address bit is set to logic zero.  
– High, that address bit is set to logic one.  
As an output pin:  
When the signal on this pin is:  
– De-asserted, this state indicates the ICS1893AF does not have a  
link.  
– Asserted, this state indicates the ICS1893AF has a valid link.  
Caution: This pin must not float. (See the notes at Section 9.2.2,  
“Multi-Function (Multiplexed) Pins: PHY Address and LED  
Pins”.)  
ICS1893AF
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
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