ICS1892
TSD
Chapter 8 Management Register Set
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
8.6 Register 4: Auto-Negotiation Register
Table 8-11 lists the bits for the Auto-Negotiation Register. An STA uses this register to select the ICS1892
capabilities that it wants to advertise to its remote link partner. During the auto-negotiation process, the
ICS1892 advertises (that is, exchanges) capability data with its remote link partner by using a pre-defined
Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged between PHYs,
when the ICS1892 has its Auto-Negotiation sublayer enabled. The value of the Link Control Word is
established based on the value of the bits in this register.
Note: For an explanation of acronyms used in Table 8-5, see Chapter 1, “Abbreviations and Acronyms”.
Table 8-11. Auto-Negotiation Advertisement Register (register 4 [0x04])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF De- Hex
fault
4.15 Next Page
Next page not supported
Always 0
Next page supported
N/A
R/W
CW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0†
0
0
1
E
1
4.14 IEEE reserved
4.13 Remote fault
4.12 IEEE reserved
4.11 IEEE reserved
4.10 IEEE reserved
4.9 100Base-T4
Locally, no faults detected
Always 0
Local fault detected
N/A
R/W
CW
0†
0†
0†
0
Always 0
N/A
CW
Always 0
N/A
CW
Always 0. (Not supported.)
N/A
CW
4.8 100Base-TX, full duplex Do not advertise ability
4.7 100Base-TX, half duplex Do not advertise ability
Advertise ability
Advertise ability
Advertise ability
Advertise ability
Note 1
Note 1
Note 1
Note 1
CW
1
1
4.6 10Base-T, full duplex
4.5 10Base-T half duplex
4.4 Selector Field bit S4
4.3 Selector Field bit S3
4.2 Selector Field bit S2
4.1 Selector Field bit S1
4.0 Selector Field bit S0
Do not advertise ability
Do not advertise ability
1
1
IEEE 802.3-specified default N/A
IEEE 802.3-specified default N/A
IEEE 802.3-specified default N/A
IEEE 802.3-specified default N/A
0
CW
0
CW
0
CW
0
N/A
IEEE 802.3-specified
default
CW
1
† As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
Note 1:
• In Hardware mode (that is, HW/SW pin is logic zero), this bit is a Read-Only bit.
• In Software mode (that is, HW/SW pin is logic one), this bit is a Command Override Write bit.
8.6.1 Next Page (bit 4.15)
This bit indicates whether the ICS1892 uses the Next Page Mode functions during the auto-negotiation
process. If bit 4.15 is logic:
• Zero, then the ICS1892 indicates to its remote link partner that these features are disabled. (Although
the default value of this bit is logic zero, the ICS1892 does support the Next Page function.)
• One, then the ICS1892 advertises to its remote link partner that this feature is enabled.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
