ICS1892
TSD
Chapter 8 Management Register Set
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
8.6.4.1 Technology Ability Field: Hardware Mode
When the ICS1892 is operating in Hardware mode (that is, the HW/SW pin is logic zero), these TAF bits are
Read Only bits. The default value of these bits depends on the signal level on the HW/SW pin and whether
the Auto-Negotiation sublayer is enabled.
In Hardware mode, with the ANSEL pin pulled:
• Low to a disabled state, the ICS1892 does not execute the auto-negotiation process. Upon completion
of the initialization sequence, the port proceeds to the idle state and begins ‘sending idles’ according to
the technology mode selected by the 10/100SEL pin and the DPXSEL pin. In this mode, the value of the
TAF bits (bits 4.8:5) are undefined.
• High to an enabled state, the ICS1892 executes the auto-negotiation process and advertises its
capabilities to the remote link partner. The 10/100SEL and DPXSEL input pins determine the single
capability that the ICS1892 advertises. The ICS1892 updates the Auto-Negotiation Advertisement
Register TAF field to indicate the pin selection. The ICS1892 sets only one of these four bits to logic one.
The other three are a logic zero.
Note: The ICS1892 does not alter the value of the Status Register bits. Although the ICS1892 is
advertising only one technology, the ISO/IEC definitions for the Status Register bits require
these bits to indicate all the capabilities of the ICS1892.
8.6.4.2 Technology Ability Field: Software Mode
In Software mode (that is, the HW/SW pin is logic one), these TAF bits are Command Override Write bits.
The default value of these bits depends on the signal level on the HW/SW pin and whether the
Auto-Negotiation sublayer is enabled.
In Software mode, with the Auto-Negotiation Enable bit (bit 0.12) set to logic:
• Zero (that is, disabled), the ICS1892 does not execute the auto-negotiation process. Upon completion of
the initialization sequence, the port proceeds to the idle state and begins transmitting idles. Two Control
Register bits – the Data Rate Select bit (bit 0.13), and the Duplex Select bit (bit 0.8) – determine the
technology mode that the ICS1892 uses for data transmission and reception. In this mode, the values of
the TAF bits (bits 4.8:5), are undefined.
• One (that is, enabled), the ICS1892 executes the auto-negotiation process and advertises its capabilities
to the remote link partner. The TAF bits (bits 4.8:5), determine the capabilities that the ICS1892
advertises to its remote link partner. For the ICS1892, all of these bits 4.8:5 are set to logic one,
indicating the ability of the ICS1892 to provide these technologies.
Note:
1. The ICS1892 does not alter the value of the Status Register bits based on the TAF bits in register
4, as the ISO/IEC definitions for the Status Register bits require these bits to indicate all the
capabilities of the ICS1892.
2. In this mode, an STA can alter the default TAF bit settings, 4.12:5, and subsequently issue an
Auto-Negotiation Restart.
8.6.5 Selector Field (Bits 4.4:0)
When its Auto-Negotiation Sublayer is enabled, the ICS1892 transmits its link capabilities to its remote Link
Partner during the auto-negotiation process. The Selector Field is transmitted based on the value of bits
4.4:0. These bits indicate to the remote link partner the type of message being sent during the
auto-negotiation process. The ICS1892 supports IEEE Std 802.3, represented by a value of 00001b in bits
4.4:0. The ISO/IEC 8802-3 standard defines the Selector Field technologies in Annex 28A.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
