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1892Y-14 参数 Datasheet PDF下载

1892Y-14图片预览
型号: 1892Y-14
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 148 页 / 1762 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS1892  
10Base-T/100Base-TX Integrated PHYceiver™  
TSD  
5.1 Reset Operations  
This section first discusses reset operations in general and then specific ways in which the ICS1892 can be  
configured for various reset options.  
5.1.1 General Reset Operations  
The following reset operations apply to all the specific ways in which the ICS1892 can be reset, which are  
discussed in Section 5.1.2, “Specific Reset Operations”.  
5.1.1.1 Entering Reset  
When the ICS1892 enters a reset condition (either through hardware, power-on reset, or software), it does  
the following:  
1. Isolates the MAC/Repeater Interface input pins  
2. Drives all MAC/Repeater Interface output pins low  
3. Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)  
4. Initializes all its internal modules and state machines to their default states  
5. Enters the power-down state  
6. Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management  
Register bits to their default values  
5.1.1.2 Exiting Reset  
When the ICS1892 exits a reset condition, it does the following:  
1. Exits the power-down state  
2. Latches the Serial Management Port Address of the ICS1892 into the Extended Control Register, bits  
16.10:6. [See Section 8.11.3, “PHY Address (bits 16.10:6)”.]  
3. Enables all its internal modules and state machines  
4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their  
associated ICS1892 input pins, as determined by the HW/SW pin  
5. Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN)  
6. Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock  
(TXCLK) and receive clock (RXCLK)  
7. Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition  
is removed  
5.1.1.3 Hot Insertion  
As with the ICS 1890, the ICS1892 reset design supports ‘hot insertion’ of its MII. (That is, the ICS1892 can  
connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the  
MAC/repeater.)  
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™  
ICS1892  
18  
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