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1892Y-14 参数 Datasheet PDF下载

1892Y-14图片预览
型号: 1892Y-14
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 148 页 / 1762 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS1892  
TSD  
10Base-T/100Base-TXIntegrated PHYceiver™  
9.2.4 MAC/Repeater Interface Pins  
This section lists pin descriptions for each of the following interfaces  
Section 9.2.4.1, “MAC/Repeater Interface Pins for Media Independent Interface”  
Section 9.2.4.2, “MAC/Repeater Interface Pins for 100M Symbol Interface”  
Section 9.2.4.3, “MAC/Repeater Interface Pins for 10M Serial Interface”  
Section 9.2.4.4, “MAC/Repeater Interface Pins for Link Pulse Interface”  
9.2.4.1 MAC/Repeater Interface Pins for Media Independent Interface  
Table 9-6 lists the MAC/Repeater Interface pin descriptions for the MII.  
Table 9-6. MAC/Repeater Interface Pins: Media Independent Interface (MII)  
Pin  
Pin  
Pin  
Pin Description  
Name Number  
Type  
COL  
49  
Output Collision (Detect).  
The ICS1892 asserts a signal on the COL pin when the ICS1892 detects  
receive activity while transmitting (that is, while the TXEN signal is  
asserted by the MAC/repeater, that is, when transmitting). When the  
mode is:  
10Base-T, the ICS1892 detects receive activity by monitoring the  
un-squelched MDI receive signal.  
100Base-TX, the ICS1892 detects receive activity when there are two  
non-contiguous zeros in any 10-bit symbol derived from the MDI  
receive data stream.  
Note:  
1. The signal on the COL pin is not synchronous to either RXCLK or  
TXCLK.  
2. In full-duplex mode, the COL signal is disabled and always remains  
low.  
3. The COL signal is asserted as part of the signal quality error (SQE)  
test. This assertion can be suppressed with the SQE Test Inhibit bit (bit  
18.2).  
CRS  
MDC  
50  
31  
Output Carrier Sense.  
In half-duplex mode, the ICS1892 asserts a signal on the CRS pin  
when the ICS1892 detects either receive or transmit activity.  
In full-duplex mode and Repeater mode, the ICS1892 asserts a signal  
on the CRS pin only when the ICS1892 detects receive activity.  
Note: The signal on the CRS pin is not synchronous to either RXCLK or  
TXCLK.  
Input  
Management Data Clock.  
The ICS1892 uses the signal on the MDC pin to synchronize the transfer  
of management information between the ICS1892 and the Station  
Management Entity (STA), using the serial MDIO data line. The MDC  
signal is sourced by the STA.  
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™  
ICS1892  
109  
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