ICS1522
User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator
ICS1522
TSD
REG#
5
BIT(S)
4-5
BIT REF.
PDA(0:1)
DESCRIPTION
Output Post-scaler (Default=0)
Input=VCO; Output = Differential Output
PFD(2)
PFD(0)
DIVIDE BY
0
0
1
1
0
1
0
1
8
4
2
1
5
6-7
PDB(0:1)
Feedback Post-scaler (Default=3)
Input=Feedback Divider; Output=PFD
PDB(1)
PDB(0)
DIVIDE BY
0
0
1
1
0
1
0
1
8
4
2
1
5
8
LD_LG
Fine Phase Adjust Lead/Lag (Default=1)
1=FBK will lag REF at input to PFD
0=FBK will lead REF at input to PFD
Fine Phase Adjust Enable (Default=))
0=Disable; 1=Enable
Must be set to one.
Load Counter (Default=7)
L(2)
L(1)
L(0)
DIVIDE BY
5
9
F_EN
5
6
10
0-2
RESERVED
L(0:2)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
31-pos, 0-neg
4 pos edge
4 neg edge
51-neg, 0-pos
6 pos edge
8 neg edge
8 neg edge
10 neg edge
7
IDT™ / ICS™
User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator
7
ICS1522
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
