ICS1522
User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator
ICS1522
TSD
ICS1522 Register Definition
REG#
0
BIT(S)
0-10
BIT REF.
F[0:10]
DESCRIPTION
Feedback Divider (Default=04F, Modulus=80) Divides the VCO
by the set modulus Modulus Range=64 to 2048;
Modulus=Value+1
Feedback Sync Pulse LO (Default=03) Feedback Divider output,
but with programmable phase; LO[0:7] <F[3:10].
Feedback Sync Pulse HI (Default=06) Feedback Divider output,
but with programmable phase; HI[0:7] <F[3:10].
Reference Divider (Default=013, Modulus=20) Divides the
XTAL/EXTREF by the set modulus Modulus Range=1 to 1024;
Modulus=Value+1
External Reference Polarity (Default=0) 0=Positive Edge;
1=Negative Edge
VCO Gain (Default=4)
VCO(2)
VCO(1)
VCO(0)
VCO GAIN
1
2
3
0-7
0-7
0-9
LO[0:7]
HI[0:7]
R[0:9]
3
4
10
0-2
REF_POL
VCO[0:2]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10 MHz/V
15 MHz/V
20 MHz/V
25 MHz/V
45 MHz/V
60 MHz/V
75 MHz/V
90 MHz/V
5
IDT™ / ICS™
User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator
5
ICS1522
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
