IDT1339
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
RTC
Address Map
Table 3 (Timekeeper Registers) shows the address map for the IDT1339 registers. During a multibyte access, when the
address pointer reaches the end of the register space (10h), it wraps around to location 00h. On an I
2
C START, STOP, or
address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read
the registers in case of an update of the main registers during a read.
Table 3. Timekeeper Registers
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
A1M1
A1M2
Bit 7
0
0
0
0
0
Century
12/24
0
0
0
10 year
10 seconds
10 minutes
AM/PM
09h
0Ah
0Bh
A1M3
A1M4
A2M2
12/24
DY/DT
10 hour
10 hour
Hour
Day, Date
Minutes
Alarm 1 Hours
Alarm 1 Day,
Alarm 1 Date
Alarm 2
Minutes
Alarm 2 Hours
Alarm 2 Day,
Alarm 2 Date
A1IE
A1F
ROUT0
Control
Status
Trickle Charger
0
Bit 6
Bit 5
10 seconds
10 minutes
AM/PM
10 hour
0
10 date
10 month
10 hour
0
0
Date
Month
Year
Seconds
Minutes
Hour
Day
Hours
Day
Date
Month/Century
Year
Alarm 1
Seconds
Alarm 1
Minutes
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Seconds
Minutes
Range
00 - 59
00 - 59
1 - 12
+ AM/PM
00 - 23
1-7
01 - 31
01 - 12 +
Century
00 - 99
00 - 59
00 - 59
1 - 12
+ AM/PM
00 - 23
1 - 7, 1 - 31
00 - 59
1 - 12
+ AM/PM
00 - 23
1 - 7, 1 - 31
Seconds
Minutes
10 date
10 minutes
AM/PM
0Ch
0Dh
0Eh
0Fh
10h
A2M3
A2M4
EOSC
OSF
TCS3
12/24
DY/DT
0
0
TCS2
10 hour
10 hour
Hour
Day, Date
RS1
0
DS1
INTCN
0
DS0
A2IE
A2F
ROUT1
10 date
BBSQI
0
TCS1
RS2
0
TCS0
Note:
Unless otherwise specified, the state of the registers are not defined when power is first applied or when V
CC
and V
BACKUP
falls
below the V
BACKUP(min)
.
IDT®
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
6
IDT1339
REV K 032910
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
