IDT1339
REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
RTC
Note 7: Using recommended crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX)
tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released.
+
Note 12: CB—total capacitance of one bus line in pF.
Note 13: Guaranteed by design. Not production tested.
Note 14: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the
voltage range of 0.0V < VCC VCCMAX and 1.3 V < VBACKUP < 3.7 V.
<
Timing Diagram
IDT® REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
18
IDT1339
REV K 032910
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
