IS61C632A
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4
-5
-6
-7
-8
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max. Unit
tKC
tKH
tKL
Cycle Time
8
—
—
—
4
10
—
—
—
5
12
—
—
—
6
13
—
—
—
7
15
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
ns
Clock High Time
4
4
4
6
6
Clock Low Time
4
4
4
6
6
tKQ
tKQX
Clock Access Time
—
1.5
0
—
1.5
0
—
2
—
2
—
2
(4)
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
—
—
4
—
—
5
—
—
6
—
—
6
—
—
6
(4,5)
tKQLZ
0
0
0
(4,5)
tKQHZ
tOEQ
1.5
—
0
1.5
—
0
2
2
2
4.5
—
—
4.5
—
—
—
—
—
—
—
—
—
5
—
0
6
—
0
6
—
0
6
(4)
tOEQX
—
—
4.8
—
—
—
—
—
—
—
—
—
—
—
6
—
—
6
—
—
6
(4,5)
tOELZ
0
0
0
0
0
(4,5)
tOEHZ
tAS
—
2.5
2.5
2.5
0.5
0.5
0.5
2
—
2.5
2.5
2.5
0.5
0.5
0.5
2
—
2.5
2.5
2.5
0.5
0.5
0.5
2
—
2.5
2.5
2.5
0.5
0.5
0.5
2
—
2.5
2.5
2.5
0.5
0.5
0.5
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tSS
Address Status Setup Time
Chip Enable Setup Time
Address Hold Time
tCES
tAH
tSH
Address Status Hold Time
Chip Enable Hold Time
ZZ Standby(1)
ZZ Recovery(2)
Configuration Setup(3)
tCEH
tZZS
tZZREC
tCFG
2
2
2
2
2
25
35
45
52
60
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Configuration signal MODE is static and must not change during normal operation.
4. Guaranteed but not 100% tested. This parameter is periodically sampled.
5. Tested with the load in Figure 2.
14
Integrated Circuit Solution Inc.
SSR001-0B
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
