®
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
ISSI
samebank.ThePRECHARGEcommandshouldbeissued
xcyclesbeforetheclockedgeatwhichthelastdesireddata
elementisvalid,wherexequalstheCASlatencyminusone.
ThisisshownintheREADtoPRECHARGEdiagramforeach
possible CAS latency; data elementn + 3 is either the last of
a burst of four or the last desired of a longer burst. Following
thePRECHARGEcommand,asubsequentcommandtothe
same bank cannot be issued until tRP is met. Note that part
of the row precharge time is hidden during the access of the
last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same opera-
tion that would result from the same fixed-length burst with
auto precharge. The disadvantage of the PRECHARGE
commandisthatitrequiresthatthecommandandaddress
buses be available at the appropriate time to issue the
command;theadvantageofthePRECHARGEcommandis
that it can be used to truncate fixed-length or full-page
bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
providedthatautoprechargewasnotactivated.TheBURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possibleCASlatency;dataelementn+3isthelastdesired
data element of a longer burst.
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
06/01/02
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
