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IS42S16800A-10T 参数 Datasheet PDF下载

IS42S16800A-10T图片预览
型号: IS42S16800A-10T
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆×8 , 8Meg X16和4Meg ×32 128兆位同步DRAM [16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 66 页 / 553 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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®
IS42S81600A, IS42S16800A, IS42S32400A  
IS42LS81600A, IS42LS16800A, IS42LS32400A  
ISSI  
Initialization  
FUNCTIONAL DESCRIPTION  
SDRAMs must be powered up and initialized in a  
predefinedmanner.  
The128MbSDRAMsarequad-bankDRAMswhichoperate  
at 2.5V or 3.3V and include a synchronous interface (all  
signals are registered on the positive edge of the clock  
signal,CLK).Eachofthe16,777,216-bitbanksisorganized  
as 4,096 rows by 256 columns by 16 bits.  
The128MSDRAMisinitializedafterthepowerisappliedto  
VDD and Vddq (simultaneously) and the clock is stable.  
A 200µs delay is required prior to issuing any command  
other than a COMMAND INHIBIT or aNOP. The COMMAND  
INHIBITorNOPmaybeappliedduringthe100usperiodand  
should continue at least through the end of the period.  
Read and write accesses to the SDRAM are burst oriented;  
accesses start at a selected location and continue for a  
programmed number of locations in a programmed  
sequence. Accesses begin with the registration of an AC-  
TIVEcommandwhichisthenfollowedbyaREADorWRITE  
command. The address bits registered coincident with the  
ACTIVE command are used to select the bank and row to  
With at least one COMMAND INHIBIT or NOP command  
havingbeenapplied,aPRECHARGEcommandshouldbe  
appliedoncethe100µsdelayhasbeensatisfied. Allbanks  
mustbeprecharged. Thiswillleaveallbanksinanidlestate  
wheretwoAUTOREFRESHcyclesmustbeperformed. After  
theAUTOREFRESHcyclesarecomplete,theSRDRAMisthen  
readyformoderegisterprogramming.  
beaccessed(BA0andBA1selectthebank,A0-A11selecttherow)  
.
Theaddressbits(A0-A7)registeredcoincidentwiththeREAD  
orWRITEcommandareusedtoselectthestartingcolumn  
location for the burst access.  
Themoderegisterandextendedmoderegistersshouldbe  
loadedpriortoapplyinganyoperationalcommandbecause  
it will power up in an unknown state.  
Prior to normal operation, the SDRAM must be initialized.  
The following sections provide detailed information covering  
device initialization, register definition, command  
descriptions and device operation.  
24  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
ADVANCEDINFORMATION Rev. 00A  
06/01/02  
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