IC42S16100
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T260
T261
T262
T263
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
t
AS
AS
tAH
COLUMN
ROW
ROW
A0-A9
t
t
AH
AH
A10
A11
NO PRE
BANK 0
BANK 0 OR 1
BANK 0
t
AS
BANK 0
t
CH
t
CS
t
QMD
DQM
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
tOH
I/O
DOUT 0m
D
OUT 0m+1
DOUT 0m-1
DOUT 0m
DOUT 0m+1
t
LZ
t
HZ
t
RCD
t
CAC
t
RBD
(BANK 0)
t
RP
t
RAS
(BANK 0)
t
RC
(BANK 0)
<
BST
>
<PRE 0>
<
ACT 0>
<
READ0>
Undefined
Don’t Care
CAS latency = 2, burst length = full page
Note 1: A8,A9 = Don't Care.
42
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004