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IC41LV16105S-50T 参数 Datasheet PDF下载

IC41LV16105S-50T图片预览
型号: IC41LV16105S-50T
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×16 ( 16兆位)动态RAM具有快速页面模式 [1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE]
分类和应用: 存储内存集成电路光电二极管动态存储器
文件页数/大小: 18 页 / 199 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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IC41C16105S  
IC41LV16105S  
ꢀunctional Description  
Write Cycle  
The IC41C16105S and IC41LV16105S is a CMOS DRAM  
optimized for high-speed bandwidth, low power  
applications. During READ or WRITE cycles, each bit is  
uniquely addressed through the 10 address bits. These  
are entered ten bits (A0-A9) at a time. The row address is  
latched by the Row Address Strobe (RAS). The column  
address is latched by the Column Address Strobe (CAS).  
RAS is used to latch the first ten bits and CAS is used the  
latter ten bits.  
A write cycle is initiated by the falling edge of CAS and WE,  
whichever occurs last. The input data must be valid at or  
before the falling edge of CAS or WE, whichever occurs  
last.  
Refresh Cycle  
To retain data, 1,024 refresh cycles are required in each  
16 ms period. There are two ways to refresh the memory.  
1. By clocking each of the 1,024 row addresses (A0  
through A9) with RAS at least once every 16 ms. Any  
read, write, read-modify-write or RAS-only cycle re-  
freshes the addressed row.  
The ICS41C16105S and IC41LV16105S has two CAS  
controls, LCAS and UCAS. The LCAS and UCAS inputs  
internally generates a CAS signal functioning in an iden-  
tical manner to the single CAS input on the other 1M x 16  
DRAMs. The key difference is that each CAS controls its  
corresponding I/O tristate logic (in conjunction with OE  
and WE and RAS). LCAS controls I/O0 through I/O7 and  
UCAS controls I/O8 through I/O15.  
2. Using a CAS-before-RAS refresh cycle. CAS-before-  
RAS refresh is activated by the falling edge of RAS,  
while holding CAS LOW. In CAS-before-RAS refresh  
cycle, an internal 10-bit counter provides the row  
addresses and the external address inputs are ignored.  
The IC41C16105S and IC41LV16105S CAS function is  
determined by the first CAS (LCAS or UCAS) transitioning  
LOW and the last transitioning back HIGH. The two CAS  
controls give the IS41C16105L and IS41LV16105L both  
BYTE READ and BYTE WRITE cycle capabilities.  
CAS-before-RAS is a refresh-only mode and no data  
access or device selection is allowed. Thus, the output  
remains in the High-Z state during the cycle.  
Self Refresh Cycle  
The Self Refresh allows the user a dynamic refresh, data  
retention mode at the extended refresh period of 128 ms.  
i.e., 125 µs per row when using distributed CBR refreshes.  
The feature also allows the user the choice of a fully static,  
low power data retention mode. The optional Self Refresh  
feature is initiated by performing a CBR Refresh cycle and  
holding RAS LOW for the specified tRAS.  
Memory Cycle  
A memory cycle is initiated by bring RAS LOW and it is  
terminated by returning both RAS and CAS HIGH. To  
ensures proper device operation and data integrity any  
memory cycle, once initiated, must not be ended or  
aborted before the minimum tRAS time has expired. A new  
cycle must not be initiated until the minimum precharge  
time tRP, tCP has elapsed.  
The Self Refresh mode is terminated by driving RAS HIGH  
for a minimum time of tRP. This delay allows for the  
completion of any internal refresh cycles that may be in  
process at the time of the RAS LOW-to-HIGH transition. If  
the DRAM controller uses a distributed refresh sequence,  
a burst refresh is not required upon exiting Self Refresh.  
Read Cycle  
A read cycle is initiated by the falling edge of CAS or OE,  
whichever occurs last, while holding WE HIGH. The  
column address must be held for a minimum time specified  
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC  
and tOEA are all satisfied. As a result, the access time is  
dependent on the timing relationships between these  
parameters.  
However, if the DRAM controller utilizes a RAS-only or  
burst refresh sequence, all 1,024 rows must be refreshed  
within the average internal refresh rate, prior to the re-  
sumption of normal operation.  
Power-On  
After application of the VCC supply, an initial pause of  
200 µs is required followed by a minimum of eight initial-  
ization cycles (any combination of cycles containing a  
RAS signal).  
During power-on, it is recommended that RAS track with  
VCC or be held at a valid VIH to avoid current surges.  
4
Integrated Circuit Solution Inc.  
DR011-0A 05/23/2001