ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS9DB202 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL.VDD andVDDA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin.To achieve optimum jitter
performance, power supply isolation is required. Figure 1 illus-
trates how a 24Ω resistor along with a 10µF and a .01µF by-
pass capacitor should be connected to eachVDDA pin.
3.3V
VDD
.01µF
24Ω
VDDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
9DB202CG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 6, 2004
7
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
