Integrated
Circuit
Systems, Inc.
ICS952621
Pin Description
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PIN NAME
FS_A/REF1
FS_B/REF0
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PD#
48MHz_DOT
48MHz_USB
GND
VDD48
3V66_3/VCH
3V66_2
VDD3V66
GND
3V66_1
3V66_0
SCLK
SDATA
VttPWR_GD#
VDD
SRCCLKC
SRCCLKT
GND
CPUCLKC0
CPUCLKT0
VDDCPU
CPUCLKC1
CPUCLKT1
GND
CPUCLKC_ITP
CPUCLKT_ITP
IREF
GND
VDDA
PIN TYPE
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
OUT
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
OUT
PWR
PWR
DESCRIPTION
FS_A latched input for frequency select
Reference output, 14.318Hz
FS_B latched input for frequency select
Reference output, 14.318Hz
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used
to power down the device. The internal clocks are disabled and the VCO and
the crystal are stopped.
48.008MHz Dot clock output
48.008MHz USB clock output
Ground pin.
Power for 48MHz output buffers and fixed PLL core.
3.3V 66.66MHz clock output
VCH: 48MHz VCH clock output
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch
inputs are valid and are ready to be sampled. This is an active low input.
Power supply, nominal 3.3V
Complementary clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin.
"Complementary" clocks of differential pair CPU outputs for ITP.. These are
current mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs for ITP. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin.
3.3V power for the PLL core.
0756A—09/10/04
2
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