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ICS9169CJ-27 参数 Datasheet PDF下载

ICS9169CJ-27图片预览
型号: ICS9169CJ-27
PDF下载: 下载PDF文件 查看货源
内容描述: 频率发生器奔腾™的系统 [Frequency Generator for Pentium™ Based Systems]
分类和应用:
文件页数/大小: 8 页 / 557 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS9169C-27  
Pin Descriptions  
PIN NUMBER  
PIN NAME  
VDD  
TYPE  
DESCRIPTION  
1
PWR  
Power for device logic.  
XTAL or external reference frequency input. This input  
includes XTAL load capacitance and feedback bias for a  
12-16MHz crystal, nominally 14.31818MHz. External crystal  
load of 30pF to GND recommended for VDD power on faster  
than 2.0ms.  
2
X1  
IN  
XTAL output which includes XTAL load capacitance.  
External crystal load of 10pF to GND recommended for VDD  
power on faster than 2.0ms.  
3
X2  
OUT  
4,11,20,26  
GND  
PWR  
OUT  
Ground for device logic.  
Processor clock output which is a multiple of the input  
reference frequency.  
CPU(1)  
5
FS0  
IN  
Frequency multiplier select pins. See shared pin description.*  
CPU  
(2:5) (8:12)  
Processor clock outputs which are a multiple of the input  
reference frequency.  
6,7,9,10,15,16,17,18,19  
8
OUT  
PWR  
Power for CPU(1:6) output buffers only. Can be reduced VDD  
for 2.5V (2.375-2.62V) next generation processor clocks.  
VDDC1  
CPU(6)  
FS1  
Processor clock output which is a multiple of the input  
reference frequency internal pull up devices.  
OUT  
IN  
12  
13  
Frequency multiplier select pin. See shared pin description.*  
Processor clock output which is a multiple of the input  
reference frequency internal pull up devices.  
CPU(7)  
FS2  
OUT  
IN  
Frequency multiplier select pin. See shared pin description.*  
Power for CPU PLL, logic and CPU(7:12)output buffers. Must  
be nominal 3.3V (3.0 to 3.7V)  
14  
VDDC2  
PWR  
BUS clock outputs which are a multiple of the input  
reference clock.  
21,22,24,25,27,28  
BUS (6:1)  
OUT  
23  
29  
VDDB  
VDDF  
PWR  
PWR  
Power for BUS clock buffers BUS(1:6).  
Power for fixed clock buffer (48 MHz, 24 Mhz).  
Fixed 24MHz clock (assuming a 14.31818MHz REF  
frequency).  
30  
31  
24MHz  
48MHz  
REF  
OUT  
OUT  
OUT  
Fixed 48MHz clock (assuming a 14.31818MHz REF  
frequency).  
Fixed 14.31818MHz clock (assuming a 14.31818MHz REF  
frequency).  
32  
Selection for synchronous or asynchronous bus clock  
operation. See shared pin programming description late in this  
data sheet for further explanation.*  
BSEL  
IN  
* Internal pull-up will vary from 350K to 500K based on temperature.  
2