Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V±5%
V
DD
V
DDA
,
V
DDO
SCOPE
nPCLK
Qx
V
PP
LVCMOS
GND
Cross Points
V
CMR
PCLK
GND
-1.65V±5%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
V
V
D
IFFERENTIAL
I
NPUT
L
EVEL
V
DDO
DDO
DDO
Q0:Q7,
QFB
➤
Clock
Outputs
20%
2
2
2
DDO
Qx
2
t
cycle
n
➤
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
C
YCLE
-
TO
-C
YCLE
J
ITTER
80%
t
R
O
UTPUT
R
ISE
/F
ALL
T
IME
V
Q0:Q7
QFB
Pulse Width
t
PERIOD
odc =
t
PW
t
PERIOD
➤
t
(Ø)
tjit(Ø)
=
t
(Ø) —
t
(Ø)
mean
= Phase Jitter
(where
t
(Ø) is any random sample, and
t
(Ø)
mean
is the average
of the sampled cycles measured on controlled edges)
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
86953BYI-147
P
HASE
J
ITTER
& S
TATIC
P
HASE
O
FFSET
REV. B APRIL 23, 2004
www.icst.com/products/hiperclocks.html
5
➤
➤
DDO
t
cycle n+1
➤
V
DDO
Qy
2
t
sk(o)
O
UTPUT
S
KEW
nPCLK
80%
PCLK
20%
t
F
Q0:Q7,
QFB
V
DDO
2
t
PD
P
ROPAGATION
D
ELAY
nPCLK
2
V
OH
V
OL
V
OH
V
DDO
PCLK
FB_CLK
V
OL
2
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
