Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
Test Conditions
Minimum
Typical
Maximum
175
Units
MHz
T
ABLE
5. PLL I
NPUT
R
EFERENCE
C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
REF
Parameter
Input Reference Frequency
T
ABLE
6. AC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
PLL Mode
Output Frequency
Propagation Delay;
NOTE 1
PLL Mode
Bypass Mode
PCLK, nPCLK
Measured on rising edge
at V
DD
/2
-20
20% to 80%
100
47
50
90
2.5
Test Conditions
VCO_SEL = 1
VCO_SEL = 0
Minimum
31.25
62.50
Typical
Maximum
87.5
175
200
4
75
50
200
700
53
10
6
Units
MHz
MHz
MHz
ns
ps
ps
ps
ps
%
ms
ns
ns
t
sk(o)
t
jitter(cc)
t(Ø)
t
R
/ t
F
odc
t
LOCK
t
EN
Output Skew; NOTE 2, 4
Cycle-to-Cycle Jitter; NOTE 5
Static Phase Offset; NOTE 3, 5
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
7
t
DIS
NOTE: Termination of 50
Ω
to V
DD
/2.
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
86953BYI-147
www.icst.com/products/hiperclocks.html
4
REV. B APRIL 23, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
