ICS1893BY-10 - Release
Chapter 9 DC and AC Operating Conditions
9.5.3 Timing for Receive Clock (RXCLK) Pins
Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various
interfaces. Figure 9-4 shows the timing diagram for the time periods.
Table 9-10. MII Receive Clock Timing
Time
Parameter
Conditions
Min. Typ. Max. Units
Period
t1
RXCLK Duty Cycle
RXCLK Period
RXCLK Period
RXCLK Period
RXCLK Period
–
35
–
50
40
65
–
%
ns
ns
ns
ns
t2a
t2b
t2c
t2d
100M MII (100Base-TX)
10M MII (10Base-T)
–
400
40
–
100M Symbol Interface (100Base-TX)
10M Serial Interface (10Base-T)
–
–
–
100
–
Figure 9-4. Receive Clock Timing Diagram
t1
RXCLK
t2
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
121
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
