ICS1893BY-10 Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.2 Timing for Transmit Clock (TXCLK) Pins
Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various
interfaces. Figure 9-3 shows the timing diagram for the time periods.
Table 9-9. Transmit Clock Timing
Time
Parameter
Conditions
Min. Typ. Max. Units
Period
t1
TXCLK Duty Cycle
TXCLK Period
TXCLK Period
TXCLK Period
TXCLK Period
–
35
–
50
40
65
–
%
ns
ns
ns
ns
t2a
t2b
t2c
t2d
100M MII (100Base-TX)
10M MII (10Base-T)
–
400
40
–
100M Symbol Interface (100Base-TX)
10M Serial Interface (10Base-T)
–
–
–
100
–
Figure 9-3. Transmit Clock Timing Diagram
t1
TXCLK
t2x
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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