欢迎访问ic37.com |
会员登录 免费注册
发布采购

ICS1893CK 参数 Datasheet PDF下载

ICS1893CK图片预览
型号: ICS1893CK
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 -V的10Base -T / 100BASE - TX集成PHYceive [3.3-V 10Base-T/100Base-TX Integrated PHYceive]
分类和应用: 电信集成电路
文件页数/大小: 126 页 / 1927 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
 浏览型号ICS1893CK的Datasheet PDF文件第65页浏览型号ICS1893CK的Datasheet PDF文件第66页浏览型号ICS1893CK的Datasheet PDF文件第67页浏览型号ICS1893CK的Datasheet PDF文件第68页浏览型号ICS1893CK的Datasheet PDF文件第70页浏览型号ICS1893CK的Datasheet PDF文件第71页浏览型号ICS1893CK的Datasheet PDF文件第72页浏览型号ICS1893CK的Datasheet PDF文件第73页  
ICS1893CF Data Sheet Rev. F - Release  
Chapter 7 Management Register Set  
7.11 Register 16: Extended Control Register  
Table 7-16 lists the bits for the Extended Control Register, which the ICS1893CF provides to allow an STA  
to customize the operations of the device.  
Note:  
1. For an explanation of acronyms used in Table 7-16, see Chapter 1, “Abbreviations and Acronyms”.  
2. During any write operation to any bit in this register, the STA must write the default value to all  
Reserved bits.  
Table 7-16. Extended Control Register (register 16 [0x10])  
Bit  
Definition  
When Bit = 0  
When Bit = 1  
Ac-  
SF  
De-  
Hex  
cess  
fault  
16.15 Command Override Write Disabled  
enable  
Enabled  
RW  
SC  
0
16.14 ICS reserved  
16.13 ICS reserved  
16.12 ICS reserved  
16.11 ICS reserved  
16.10 PHY Address Bit 4  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
RW/0  
RW/0  
RW/0  
RW/0  
RO  
0
Read unspecified  
Read unspecified  
Read unspecified  
0
0
0
For a detailed explanation of this bit’s operation,  
see Section 5.5, “Status Interface”.  
P4RD†  
16.9  
16.8  
16.7  
16.6  
PHY Address Bit 3  
PHY Address Bit 2  
PHY Address Bit 1  
PHY Address Bit 0  
For a detailed explanation of this bit’s operation,  
see Section 5.5, “Status Interface”.  
RO  
RO  
RO  
RO  
P3TD†  
P2LI†  
For a detailed explanation of this bit’s operation,  
see Section 5.5, “Status Interface”.  
For a detailed explanation of this bit’s operation,  
see Section 5.5, “Status Interface”.  
P1CL†  
P0AC†  
8
For a detailed explanation of this bit’s operation,  
see Section 5.5, “Status Interface”.  
16.5  
16.4  
16.3  
16.2  
16.1  
16.0  
Stream Cipher Test Mode Normal operation  
Test mode  
RW  
RW/0  
RW  
0
1
0
0
0
ICS reserved  
Read unspecified  
NRZ encoding  
Disabled  
Read unspecified  
NRZI encoding  
Enabled  
NRZ/NRZI encoding  
Transmit invalid codes  
ICS reserved  
RW  
Read unspecified  
Read unspecified  
RW/0  
RW  
Stream Cipher disable  
Stream Cipher enabled Stream Cipher disabled  
† The default is the state of this pin at reset.  
ICS1893CF, Rev. F, 03/01/07  
Mar. 2007  
Copyright © 2007, Integrated Device Technology, Inc.  
All rights reserved.  
69  
 复制成功!