ICS1523
2
Video Clock Synthesizer with I C Programmable Delay
Section 11 Programming
2
11.1 Industry-Standard I C Serial Bus: Data Format
2
Figure 11-1 ICS1523 Data Format for I C 2-Wire Serial Bus
Write Procedure for Single Register
MSB
LSB
S
0
1
0
0
1
1
X
0
A
A
A
A Stop
Device address
Register Index
Data
Read Procedure for Single Register
MSB LSB
MSB
LSB
S
0
1
0
0
1
1
X
0
A
S
0
1
0
0
1
1
X
1
A
A
Stop
Device address
Register Index
Device address
Repeat START
Data
NO Acknow ledge
Write Procedure for Multiple Registers (Note 1)
MSB LSB
S
0
1
0
0
1
1
X
0
A
A
A
A
A
A
A
Stop
Stop
Device address
Register Index
Data
Data
Data
Read Procedure for Multiple Registers (Note 1)
MSB LSB
MSB
LSB
S
0
1
0
0
1
1
X
0
A
S
0
1
0
0
1
1
X
1
A
A
Device address
Register Index
Device address
Repeat START
Data
NO Acknow ledge
Legend
All values are sent with the most-significant bit (MSB) first and least-significant bit (LSB) last.
= Read = 1
R
W = Write = 0
S
= Start (SDA goes low when SCL was high, then SCL goes low too)
A = ACK = Acknowledge = 0
A = ACK = No Acknowledge = 1
X
= Bit value that equals logic state of SBADR pin.
= (Dashed Line) Multiple transactions
Bus Master drives signal to ICS1523
ICS1523 (Slave Device) drives signal to Bus Master
Note:
2
• 1 - Lower nibble of the I C register automatically increments after each successive data byte is written to
or read from the ICS1523.
2
• 2 - Upper nibble of the I C register does not automatically increment, and the software must explicitly
re-address the ICS1523. The software:
– Must NOT just index 0 and then do all the I/O as one-byte transactions.
– Must break the transactions into at least two separate bus transactions:
(1) 00 to 08 (2) 10 to 12
MDS 1523 Y
12
Revision 110905
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